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Accelerating Deep Learning Algorithms using FPGA FDP 2026 at SDMCET Dharwad (Free)
Applications are now open for the AICTE Training and Learning (ATAL) Academy sponsored Faculty Development Programme on Accelerating Deep Learning Algorithms using FPGA FDP 2026. Themed “Accelerating Deep Learning Algorithms using FPGA for Tumour and Lesion detection”, this week-long offline workshop is organized by the Department of Electronics and Communication Engineering at Shri Dharmasthala Manjunatheshwara College of Engineering & Technology (SDMCET), Dharwad, Karnataka.
Scheduled to take place from September 21 to September 26, 2026, this FDP provides in-depth insights into disease detection, medical image analysis, Convolutional Neural Networks (CNNs), and real-time hardware acceleration using Field Programmable Gate Arrays (FPGAs). There is no registration fee for selected participants.
Program Details Overview
| Feature | Details |
| Program Title | Accelerating Deep Learning Algorithms using FPGA for Tumour and Lesion detection |
| Host Institution | SDM College of Engineering and Technology (SDMCET), Dharwad, Karnataka |
| Organizing Department | Department of Electronics and Communication Engineering |
| Sponsorship | All India Council for Technical Education (AICTE), New Delhi under ATAL Scheme |
| Program Dates | September 21 to September 26, 2026 |
| Mode of Conduction | Offline |
| Registration Fee | Free (Sponsored by AICTE ATAL) |
| Institutional Status | Autonomous, Affiliated to VTU Belagavi, Accredited by NBA |
Objectives and Core Focus Areas
The Accelerating Deep Learning Algorithms using FPGA FDP 2026 focuses on optimizing hardware implementation for medical AI applications, reducing misdiagnosis risks, and achieving lower power consumption compared to standard GPU/CPU deployments.
Major Course Contents:
- Digital Image Processing: Image filter design and medical image enhancement.
- Medical AI Case Studies: Tumor and lesion identification in X-rays, CT scans, and MRIs.
- Programming & Deep Learning: Python fundamentals and Convolutional Neural Network (CNN) architectures.
- FPGA Acceleration: Accelerating CNNs on FPGA-powered platforms and optimizing resource utilization.
- Hardware Design Flow: System Generator design flow, hardware configuration, and real-time FPGA deployment.
Resource Persons
Sessions will be conducted by eminent academicians, scientists, and industry experts drawn from premier institutions such as IITs, IISc, NITs, research laboratories, and leading technology organizations.
Eligibility Criteria & Certification Requirements
Target Audience:
- Faculty members and Research Scholars from AICTE-recognized institutions.
- Delegates, engineers, and scientists from relevant technology industries and research organizations.
Evaluation & ATAL Certification:
In accordance with AICTE ATAL Academy norms, an official certificate of completion will be granted to participants who maintain mandatory attendance standards and perform successfully in continuous assessments across the six-day duration.
Important Dates
| Event | Date |
| Last Date of Registration | August 31, 2026 |
| Intimation of Selection | September 3, 2026 |
| FDP Conduction Period | September 21 to September 26, 2026 |
Step-by-Step How to Apply
- Access the official online registration form via the Google Form Link. (Note: Applicants must use a valid Gmail ID for registration).
- Fill in your personal, academic, and institutional details accurately.
- Cross-register on the official AICTE ATAL Academy Portal.
- Submit your application before the August 31, 2026 deadline.
Important Links
| Resource | Link / Details |
| Registration Form | Google Form Registration Link |
| Official Registration Portal | AICTE ATAL Portal |
| Download FDP Brochure | Download |
| Download FDP Schedule | Download |
| Official Institute Website | SDMCET Dharwad |
Contact Details
| Resource | Link / Details |
| FDP Coordinator (Dr. Satish S. Bhairannawar) | Professor & Dean III, Dept. of ECE (Phone: 9986008419) |
| FDP Co-Coordinator (Mrs. Reshma Nadaf) | Assistant Professor, Dept. of ECE (Phone: 9742271757) |
| Institute Landline & Fax | Phone: 0836-2447465 / Fax: 0836-2464638 |
FAQs
Is there a fee to attend the Accelerating Deep Learning Algorithms using FPGA FDP 2026?
No, there is no registration fee. The workshop is fully sponsored by the AICTE ATAL Academy.
Why are FPGAs used instead of GPUs for deep learning in tumor detection?
FPGAs optimize resource utilization, leading to lower power consumption, smaller footprints, and real-time processing capabilities suitable for resource-constrained medical environments.
What is the last date to register for this FDP?
The last date for submitting your registration form is August 31, 2026.