Integrating Machine Learning into VLSI Design Flow FDP 2026 at SVPCET Puttur (Free)

Applications are now open for the AICTE Training and Learning (ATAL) Academy sponsored Faculty Development Programme on Integrating Machine Learning into VLSI Design Flow and RTL-to-GDSII Automation. Organized by the Department of Electronics and Communication Engineering (ECE) at Sri Venkatesa Perumal College of Engineering and Technology (SVPCET), Puttur, Andhra Pradesh, this one-week national-level offline workshop will be held from September 14 to September 19, 2026.

The program serves as a collaborative platform for academicians, researchers, and industry professionals to explore cutting-edge advancements in artificial intelligence and machine learning applications within semiconductor design. There is no registration fee for participants.

Program Details Overview

Feature	Details
Program Title	Integrating Machine Learning into VLSI Design Flow and RTL-to-GDSII Automation
Host Institution	Sri Venkatesa Perumal College of Engineering and Technology (SVPCET), Puttur, A.P.
Organizing Department	Department of Electronics and Communication Engineering (ECE)
Sponsorship	AICTE Training and Learning (ATAL) Academy
Program Dates	September 14, 2026, to September 19, 2026
Mode of Conduction	Offline / In-Person
Registration Fee	Nil (Free of Cost)
Participant Limit	Limited to 50 Participants (First-Come, First-Served)

About the Programme & Objectives

Integrating Machine Learning (ML) into VLSI design addresses the complexity and manual overhead traditionally associated with Register Transfer Level (RTL) to GDSII design flows. By leveraging predictive modeling, design space exploration, and intelligent decision-making, ML algorithms optimize synthesis, placement, routing, timing analysis, and power consumption.

Key Objectives:

• Equip participants with knowledge and practical skills to integrate ML techniques into RTL-to-GDSII automation.
• Bridge traditional VLSI methodologies with modern AI/driven semiconductor design tools.
• Provide hands-on training on EDA tools, ML-based optimizations, and real-world intelligent chip design applications.

Topics Covered

• Overview of VLSI Design Flow (RTL-to-GDSII)
• Emerging Trends in AI/ML for Semiconductor Design
• Machine Learning Techniques for EDA Applications
• ML-Based Optimization in Synthesis, Placement, and Routing
• Power, Timing, and Area Prediction using ML Models
• AI/ML in FPGA and Embedded System Design
• ASIC Physical Design Flow and Automation Strategies
• AI/ML Tools for Semiconductor Design
• Hands-on Training with Xilinx Vivado and ML Integration
• Challenges, Research Opportunities, and Industry Applications

Eminent Resource Persons

Sessions will be conducted by expert speakers from prestigious institutions and organizations:

• Indian Institute of Technology (IIT) Tirupati
• Indian Institute of Information Technology Design and Manufacturing (IIITDM) Kancheepuram
• National Institute of Technology (NIT) Tiruchirappalli
• LEADSOC Technologies, Bangalore

Eligibility Criteria & Selection

• Target Audience: Faculty members of AICTE-approved institutions, university faculty, research scholars, government representatives, and R&D industry professionals.
• Selection Process: Limited to 50 participants on a first-come, first-served basis, with preference given to new applicants.

Important Dates

Event	Date
FDP Duration	September 14, 2026 – September 19, 2026

Step-by-Step How to Apply

1. Visit the official AICTE ATAL Portal.
2. Log in or register as a participant.
3. Search for the FDP hosted by Sri Venkatesa Perumal College of Engineering and Technology and complete your online application.

Important Links

Resource	Links
Official Registration Portal	ATAL Academy Portal
Download FDP Brochure	Download
Download FDP Schedule	Download

Contact Details

Resource	Details
Coordinator 1	Dr. M. Bharathi (Associate Professor, Dept. of ECE) – Mobile: 8985748274 / Email: bharathi891@gmail.com
Coordinator 2	Dr. S. Venkata Kiran (Professor, Dept. of ECE) – Mobile: 8333020485 / Email: venkatakiran95@gmail.com
Institution Address	Sri Venkatesa Perumal College of Engineering and Technology (SVPCET), Puttur, Tirupati District, Andhra Pradesh

FAQs

Is there any registration fee for the FDP?
No, there is no registration fee; the program is fully sponsored by the AICTE ATAL Academy.

Who is eligible to apply for Integrating Machine Learning into VLSI Design FDP 2026?
Faculty members from AICTE-approved institutions, university faculty, research scholars, industry practitioners, and R&D professionals are eligible.

What is the training mode on Integrating Machine Learning into VLSI Design FDP 2026?
The program is conducted in an offline (in-person) mode at the SVPCET campus, featuring expert lectures and hands-on tool training.