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VLSI Design for AI and Edge Computing FDP 2026 at VIT Bhimavaram (Free)
Applications are now open for the AICTE Training and Learning (ATAL) Academy sponsored Faculty Development Programme on VLSI Design for AI and Edge Computing FDP 2026. Themed “VLSI Design for AI and Edge Computing: Architectures and Optimization”, this six-day offline FDP is organized by the Department of Electronics and Communication Engineering (ECE) at Vishnu Institute of Technology (Autonomous), Bhimavaram, Andhra Pradesh.
Scheduled to take place from September 21 to September 26, 2026, this workshop provides comprehensive insights into hardware accelerators, low-power ASIC design, System-on-Chip (SoC) integration using RISC-V cores, and memory-interconnect optimization for resource-constrained edge devices. There is no registration fee for selected participants.
Program Details Overview
| Feature | Details |
| Program Title | VLSI Design for AI and Edge Computing: Architectures and Optimization |
| Host Institution | Vishnu Institute of Technology (Autonomous), Bhimavaram, Andhra Pradesh |
| Organizing Department | Department of Electronics and Communication Engineering (ECE) |
| Sponsorship | AICTE Training and Learning (ATAL) Academy |
| Program Application No. | 1775889773 |
| Program Dates | September 21 to September 26, 2026 |
| Registration Deadline | September 7, 2026 |
| Registration Fee | Nil (Free of Cost) |
| Seat Limit | Capped at 50 Participants |
Objectives and Core Modules
The VLSI Design for AI and Edge Computing FDP 2026 addresses the architectural challenges of deploying artificial intelligence at the edge, emphasizing low latency, energy efficiency, and high throughput.
Major Course Modules Covered:
- AI in VLSI Design Flow: Integrating machine learning algorithms into electronic design automation.
- ASIC & FPGA AI Accelerators: Hardware design for neural network acceleration.
- Power, Performance, and Area (PPA) Optimization: Advanced strategies for energy-efficient VLSI systems.
- System-on-Chip (SoC) Design: Implementing RISC-V open-source architecture for edge AI solutions.
- Low-Power Hardware Design: Circuit and logic optimization for resource-constrained intelligent systems.
- Advanced Semiconductor Packaging: 3D packaging, chiplets, and high-performance computing interconnects.
- Memory & Interconnect Optimization: Reducing latency and memory bottlenecks in AI chipsets.
- Industrial Exposure: Field visit to Vishva TBI (Vishnu Foundation Technology Business Incubator).
Eminent Resource Persons & Speakers
Sessions will be conducted by distinguished professors and senior industry engineers:
- Dr. Gajendranath Chaudhury CH. – Associate Professor, IIT Hyderabad
- Dr. Pankaj Kumar – Assistant Professor, IIIT Dharwad
- Dr. Balwinder Raj – Associate Professor, NIT Jalandhar
- Dr. B. Naresh Kumar Reddy – Assistant Professor, NIT Trichy
- Dr. Syed Sadique Anwer Askari – Assistant Professor, Manipal University Jaipur
- Dr. Divya Singh – Senior Design Engineer, NXP Semiconductors
- Mr. Ganesna Venkata Ramakrishna – Design Engineer, Intel Corporation, Bangalore
- Dr. C. P. Ravi Kumar – Chief Learning Officer, VinyanaTech, Bangalore
- Dr. Ramachandra – Director Technical, Four-C-Tron, Bangalore
- Dr. Vijay Mishra – Founder & CEO, EvryVed Pvt. Ltd., Bangalore
Daily Schedule Breakdown
| Session / Day | Morning Session (09:30 AM – 12:00 PM) | Afternoon Session (02:00 PM – 04:30 PM) | Practical Lab / Hands-on (04:30 PM – 05:30 PM) |
| Day 1 (21-09-2026) | S1: AI in VLSI Design Flow (Dr. Pankaj Kumar) | S2: Characterization & Manufacturing using AI (Dr. Vijay Mishra) | Lab 1: Design Verification using Verilog Vivado Tools |
| Day 2 (22-09-2026) | S3: ASIC & FPGA-Based AI Accelerators (Dr. Gajendranath Chaudhury) | S4: Power, Performance, and Area (PPA) Optimization (Dr. Balwinder Raj) | Lab 2: Schematic & Layout Design using Cadence Tools |
| Day 3 (23-09-2026) | S5: System-on-Chip Design with RISC-V (Dr. B. Naresh Kumar Reddy) | S6: Low-Power Hardware Design (Dr. Divya Singh) | Lab 3: Schematic & Layout Design using Cadence Tools |
| Day 4 (24-09-2026) | S7: Advanced Low-Power ASIC Strategies (Mr. Ganesna V. Ramakrishna) | S8: Advanced Packaging for AI (Dr. Syed Sadique Askari) | Lab 4: RTL to GDS Design Flow using Synopsys Tools |
| Day 5 (25-09-2026) | Industrial Field Visit: Vishva TBI (09:00 AM – 01:00 PM) | S9: Memory & Interconnect Optimization (Dr. C. P. Ravi Kumar) | Lab 5: Semiconductor Device Modeling & TCAD Simulation |
| Day 6 (26-09-2026) | S10: Advanced Semiconductor Packaging (Dr. Ramachandra) | MCQ Assessment Test & Reflection Journal | Valedictory Session |
Eligibility & Certification Guidelines
Target Participants:
Faculty members and Postgraduate (PG) students from AICTE-approved engineering institutions are eligible to apply.
Selection & Certificate Criteria:
- Selection is processed on a first-come, first-served basis, capped at 50 participants. Shortlisted candidates will receive email confirmations on September 14, 2026.
- An official e-certificate will be issued directly by the AICTE ATAL Academy to participants who achieve a minimum of 80% attendance, submit daily feedback forms, and score over 60% on the final assessment test.
Important Dates
| Event | Date |
| Last Date to Register | September 7, 2026 |
| Intimation to Shortlisted Candidates | September 14, 2026 |
| FDP Conduction Period | September 21 to September 26, 2026 |
Step-by-Step How to Apply
- Visit the official AICTE ATAL Portal.
- Log in or create a participant profile account.
- Search for the FDP titled “VLSI Design for AI and Edge Computing: Architectures and Optimization” using Application Number 1775889773 or filter by Vishnu Institute of Technology.
- Submit your registration request prior to the deadline on September 7, 2026.
Important Links
| Resource | Link / Details |
| Official Registration Portal | AICTE ATAL Portal |
| Download FDP Brochure | Download |
| Download FDP Schedule | Download |
| Official College Website | Vishnu Institute of Technology |
Important Links & Contact Details
| Resource | Details |
| FDP Coordinator (Dr. G. Prasanna Kumar) | Professor, Dept. of ECE (Phone: 9491966854 / Email: prasannakumar.g@vishnu.edu.in) |
| FDP Co-Coordinator (Dr. B. V. V. Satyanarayana) | Professor, Dept. of ECE (Phone: 9908891456 / Email: satyanarayana.b@vishnu.edu.in) |
| Institution Address | Vishnu Institute of Technology, Vishnupur, Bhimavaram, West Godavari District, Andhra Pradesh – 534202 |
FAQs
Is there a registration fee for the VLSI Design for AI and Edge Computing FDP 2026?
No, there is no registration fee. The workshop is fully sponsored by the AICTE ATAL Academy.
What CAD and EDA tools will be taught during the practical lab sessions?
Participants will receive hands-on training using Xilinx Vivado, Cadence, Synopsys (RTL to GDS II flow), and TCAD for semiconductor device modeling.
What is the application number to search on the ATAL portal?
The application number for this program is 1775889773.