Address
BHub, 5th Floor, Maurya Lok Complex, New Dak Bunglow Rd, , Patna, Bihar 800001
Work Hours
Monday to Friday: 9AM - 5PM
Weekend: 11AM - 3PM
Address
BHub, 5th Floor, Maurya Lok Complex, New Dak Bunglow Rd, , Patna, Bihar 800001
Work Hours
Monday to Friday: 9AM - 5PM
Weekend: 11AM - 3PM
Initiative by Scrollwell
Emerging Trends in VLSI Design PVPSIT operates as an AICTE-sponsored short-term skill training program at Prasad V Potluri Siddhartha Institute of Technology. The Department of Electronics & Communication Engineering manages this comprehensive course to deliver specialized knowledge in advanced semiconductor logic design entirely free of cost. Eligible applicants include faculty members from AICTE-approved institutions and active research scholars. Since intake remains strictly limited, candidates must complete their registrations through the centralized ATAL portal before the final closing deadline.
| Organising Body | Duration | Location or Platform |
| Department of Electronics & Communication Engineering | 6 Days | Prasad V Potluri Siddhartha Institute of Technology |
The primary goal of the instructional curriculum centers on promoting research and developmental activities within the semiconductor sector. Specifically, the Emerging Trends in VLSI Design PVPSIT modules address critical contemporary problems related to Advanced VLSI (Chip) Logic Design and Physical Design. Consequently, participants gain an excellent platform to strengthen their knowledge base in advanced technical domains.
Established in 1998, the host institution operates under the sponsorship of the Siddhartha Academy of General & Technical Education. Notably, the college attained autonomous status in 2012 and holds an NAAC A+ grade accreditation. Furthermore, its engineering branches have achieved multiple accreditation cycles from the National Board of Accreditation, demonstrating sustained compliance with high quality standards.
Academic Qualification
Experience & Other Conditions
The program offers specialized technical training sponsored by a central apex body to foster institutional research excellence.
| Component | Amount or Detail |
| Registration Fee | Nil (No registration fees required to attend) |
| Learning Opportunities | Exposure to exchange experiences via workshops, orientations, and peer mentoring |
| Event | Date |
| Programme Start Date | 24 August 2026 |
| Programme End Date | 29 August 2026 |
| Resource | Link |
| Apply Online | Click Here |
| Download FDP Brochure | Download |
| Download FDP Schedule | Download |
What is the core focus of the Emerging Trends in VLSI Design PVPSIT program?
The program primarily aims to enhance research knowledge in Advanced VLSI Logic Design, Physical Design, Nano Electronics, and Image Processing.
Is there an application fee for attending this FDP?
Notably, there are no registration fees collected from candidates to participate in this training program.
Who are the resource persons selected to deliver the technical sessions?
The expert sessions will be handled by distinguished professionals drawn from various IITs, NITs, central universities, and semiconductor industries.
How are the limited seats allocated among applicants?
The institutional selection committee reviews the submissions and allocates seats strictly on a first-come, first-served basis.
Where should applicants register for this training course?
Candidates must complete their online registration processes via the official AICTE ATAL portal or link through the host institute portal.