ATAL FDP EWIT 2026

The ATAL FDP EWIT operates as a short-term skill training program focusing on modern trends in ASIC verification using artificial intelligence and machine learning. Organized by the Department of Electronics & Communication Engineering at East West Institute of Technology, this initiative provides academic researchers and faculty members with advanced hands-on skills in VLSI EDA tools without any registration fees. Eligible applicants include engineering educators and research scholars looking to advance their design validation expertise. Interested candidates must submit their applications on a first-come, first-served basis before the final deadline.

Programme Highlights

Organising Body	Duration	Location or Platform	Last Date to Apply
Department of Electronics & Communication Engineering, East West Institute of Technology	6 Days	VLSI LAB, Ist Floor, EWIT, Bengaluru, Karnataka	First-come, first-served basis

About the Programme

The primary objective of this instructional course is to enable educators to acquire essential skills in the digital design flow of programmable ASICs integrated with intelligence modules. Specifically, the coursework introduces the core fundamentals of digital design using Verilog. Furthermore, it provides technical exposure to the complete design flow, spanning from baseline design entry to final GDSII file generation using a 45nm ASIC technology platform.

Notably, the host institute offers an expansive ecosystem well-suited for high-level technological study. Established in 2001, East West Institute of Technology features a 20-acre learning environment in Bengaluru and holds a NAAC ‘A’ grade accreditation. The core department emphasizes building long-term research competencies. Consequently, this ATAL FDP EWIT delivers the necessary tools to bridge academic teaching with modern industrial verification architectures.

Eligibility Criteria

Academic Qualification

• Candidates must be pursuing or possess technical qualifications relevant to engineering specializations.
• Scholars registered in postgraduate programs or doctoral research setups qualify for admission.

Experience & Other Conditions

• Faculty members teaching in AICTE-recognized engineering institutions constitute the primary beneficiary group.
• Research scholars engaged in electronics, VLSI design, or communication domains hold eligibility.
• Applicants must adhere to the formal submission guidelines outlined by the training academy coordinators.

Benefits & Funding

This state-sponsored initiative provides complete financial exemptions alongside official career-advancement certifications.

Component	Amount or Detail
Registration Fee	NO REGISTRATION FEE (Fully sponsored)
E-Certificate Award	Issued to participants completing attendance and test criteria

Topics / Themes Covered

• Day 1: Specs to RTL coding and writing simple test benches for design validation using Cadence tools.
• Day 2: Code coverage using Cadence IMC, RTL Synthesis, Equivalence checks via Genus/Conformal, and timing analysis.
• Day 3: Comprehensive overview of the ASIC verification process alongside System Verilog design constructs.
• Day 4: Innovations in chip verification using machine learning and System Verilog assertions.
• Day 5: Industrial visit to Nano Technology Fabrication Lab alongside an introduction to UVM methodology.
• Day 6: Final course evaluation, technical assessments, and valedictory proceedings.

Selection Process

• Chronological Screening: The organizing committee processes entries strictly on a first-come, first-served basis.
• Attendance Tracking: Participants must maintain a strict minimum of 80% attendance throughout the six days.
• Assessment Test: Candidates must secure a minimum score of 70% in the evaluation test conducted on the final day.

How to Apply

1. Log in to the official AICTE ATAL Academy portal platform.
2. Navigate to the participant registration dashboard section.
3. Search for the specific program hosted at East West Institute of Technology.
4. Fill out the mandatory personal details and institutional affiliation records accurately.
5. Complete the printed registration form with necessary signatures and submit the application online.

Important Dates

Event	Date
Last Date to Apply	Subject to seat availability
Programme Start Date	03 August 2026
Programme End Date	08 August 2026

Important Links

Resource	Link
Apply Online	Click Here
Download FDP Brochure	Download
Download FDP Schedule	Download

Contact Details

• Official Address: Department of Electronics & Communication Engineering, East West Institute of Technology, #63, Off Magadi Road, Bengaluru, Karnataka-560091.
• Phone: 080-23288899 / Mobile: 9448180805 (Dr. S G Hiremath), 9986680002 (Prof. Manjula B B).
• Email: hiremathsg@ewit.edu.in / manjulabb@ewit.edu.in.

FAQs

What is the core theme of the ATAL FDP EWIT?
The program highlights modern trends in ASIC verification by integrating artificial intelligence and machine learning methodologies.

Is there any participation charge for attending the modules?
No, the institutional organizers do not collect any registration fees from the eligible candidates.

Which software utilities will be utilized during the practical sessions?
Participants will get hands-on training using industrial VLSI EDA tools, explicitly focusing on Cadence frameworks like Genus and IMC.

Who are the main subject experts handling the technical tracks?
The sessions will be led by senior technical managers from Entuple Technologies and expert professors from IIIT Bangalore.

How are the certificates distributed to the attendees?
The coordinators award official e-certificates exclusively to those who maintain 80% attendance and achieve 70% marks in the final test.