NIT Meghalaya Junior Research Fellow Recruitment 2025 and NIT Meghalaya, Sohra (December 22, 2025)

NIT Meghalaya Junior Research Fellow Recruitment 2025 offers a prestigious opportunity for engineering and science graduates to engage in cutting-edge defense research. The Department of Electronics and Communication Engineering (ECE) is currently inviting applications for a temporary JRF position under a project funded by the Directorate of Futuristic Technology Management (DFTM), DRDO. Specifically, this role focuses on the development of advanced semiconductor sensors for extreme environments. Consequently, it represents a significant career milestone for researchers specializing in VLSI and MEMS technology.

Program Highlights

Feature	Details
Program Title & Code	JRF Recruitment (No. – DFTM/07/3603/DIA-CoE,MZU/MEMS/P-03)
Organizing Institution	National Institute of Technology (NIT) Meghalaya
Department	Electronics and Communication Engineering (ECE)
Application Deadline	January 06, 2026
Mode of Delivery	On-site Research (Sohra, Meghalaya)
Project Sponsor	DFTM, DRDO

Program Overview

The primary objective of this research project is the design and development of Silicon Carbide (SiC) MEMS-based piezoresistive and MOSFET embedded pressure sensors. These sensors are specifically engineered for high-temperature applications, where conventional silicon-based technology often fails. Furthermore, the project aims to establish robust fabrication process flows and simulation models. The National Institute of Technology Meghalaya, as an Institute of National Importance, provides the high-end infrastructure necessary for such sophisticated semiconductor research. The target audience includes motivated M.Tech or GATE-qualified candidates ready to contribute to India’s self-reliance in defense technology.

Eligibility Criteria

Interested candidates must fulfill specific academic requirements to be considered for the position. Specifically, the eligibility criteria include:

• M.Tech / M.E. in Microelectronics, VLSI, Electronics, or related technical disciplines.
• M.Sc. degree holders provided they possess a valid GATE or NET qualification.
• B.Tech / B.E. in Electronics and Communication Engineering, provided the candidate is GATE-qualified.
• Age Limit: Candidates should ideally be below 30 years of age, though relaxations apply as per institute and Government of India norms.

Curriculum & Topics Covered

The selected Junior Research Fellow will work on several high-impact research modules:

• SiC-MEMS Design: Modeling of piezoresistive structures using industry-standard simulation tools.
• MOSFET Integration: Techniques for embedding MOSFETs into MEMS-based pressure sensors.
• High-Temperature Characterization: Testing of sensors under extreme thermal conditions.
• Fabrication Process Flow: Designing the lithography and etching steps required for SiC devices.

Resource Persons

The project is led by distinguished academicians with extensive experience in Micro-Electro-Mechanical Systems:

• Dr. Pradeep Kumar Rathore: Principal Investigator (PI), Department of ECE, NIT Meghalaya.
• Prof. L. Lolit Kumar Singh: Co-Principal Investigator (Co-PI), NIT Manipur.

Learning Outcomes

Participants in this research initiative will acquire specialized technical competencies. Specifically, they will:

• Master the design and simulation of SiC-based MEMS devices.
• Gain hands-on experience in developing fabrication process flows for semiconductor sensors.
• Understand the complexities of high-temperature electronics and embedded systems.
• Develop advanced technical writing and analytical skills through project documentation.

Certification & Assessment

As this is a research fellowship, performance will be evaluated annually. The tenure is initially for two years or until the project concludes. Successful completion of the tenure provides a highly valuable experience certificate from NIT Meghalaya, which is a significant asset for those planning to pursue a PhD or industrial R&D roles.

Registration Details

Component	Information
Application Link	click here
Last Date to Apply	January 06, 2026
Registration Fee	Nil (No application fee)
Selection Criteria	Merit-based shortlisting followed by Interview
Interview Date	January 12, 2026 (Tentative)
Notification of Shortlist	January 09, 2026

Contact Information

For queries regarding the application process or project details, candidates may contact:

• Coordinator: Dr. Pradeep Kumar Rathore
• Email: pradeeprathore@nitm.ac.in (CC to llksingh@nitmanipur.ac.in)
• Address: Room No 210, Block-D, NIT Meghalaya, Saitsohpen, Sohra, East Khasi Hills, Meghalaya – 793108.

Additional Information

NIT Meghalaya provides hostel accommodation or HRA as per institute norms. Candidates must submit a single merged PDF containing the filled application form and all supporting academic documents. Furthermore, applicants must ensure they have a stable internet connection if the interview is conducted in online mode.

Key Highlights

• DRDO Sponsored: Work on high-priority defense technology projects.
• PhD Opportunity: Selected candidates may be eligible to register for a PhD at NIT Meghalaya as per institute norms.
• Specialized Facilities: Access to the MEMS Computing Laboratory and advanced EDA tools.

Frequently Asked Questions (FAQs)

Is a GATE score mandatory for B.Tech applicants?
Yes, B.Tech/B.E. candidates must have a valid GATE qualification to be eligible for the NIT Meghalaya Junior Research Fellow Recruitment 2025.

What is the monthly fellowship amount?
The selected JRF will receive a monthly stipend of ₹37,000 plus HRA or accommodation according to the institute’s prevailing norms.

How should I submit my application?
You must send the soft copy of your filled application and merged documents to pradeeprathore@nitm.ac.in with a CC to llksingh@nitmanipur.ac.in.

When will the interview take place?
The tentative date for the interview or examination is January 12, 2026. Only shortlisted candidates will receive an email invitation.

Can I apply if I have an M.Sc. in Physics?
M.Sc. candidates are eligible provided they have a valid GATE or NET qualification and a background relevant to the project’s electronics and communication requirements.